Generally, semiconductor dies comprise active devices, metallization layers forming connections to the active devices, and I/O contacts to provide the metallization layers (and active devices) signals and power. The metallization layers generally comprise a series of dielectric layers and metal layers in order to provide all of the required connections between the active devices and the I/O contacts (and between individual active devices). These dielectric layers may be formed from low-k dielectric materials with dielectric constants (k value) between about 2.9 and 3.8, ultra low-k (ULK) dielectric materials, with k values less than about 2.5, or even extra low-k (ELK) dielectric materials with k values between about 2.5 and about 2.9, or some combination of low-k dielectric materials.
However, while these low-k, ULK, and ELK materials may be used to improve the electrical characteristics of the metallization layers and thereby increase the overall speed or efficiency of the semiconductor device, these materials may also exhibit structural deficiencies. For example, some of these materials may have greater trouble than other dielectric materials handling the stresses applied to them in the semiconductor device. As such, the low-k, ULK, and ELK materials tend to delaminate or crack when too much pressure is applied to the low-K, ELK, and ULK materials, thereby damaging or destroying the semiconductor device and reducing yields and increasing costs.
These delamination issues related to stress can be particularly troublesome when using packaging techniques such as surface-mount technology (SMT) and flip-chip packaging. As opposed to more conventional packaged ICs that have a structure basically interconnected by fine gold wire between metal pads on the die and electrodes spreading out of molded resin packages, these packaging techniques rely on bumps of solder to provide an electrical connection between contacts on the die and contacts on a substrate, such as a packaging substrate, a printed circuit board (PCB), another die/wafer, or the like. The different layers making up the interconnection typically have different coefficients of thermal expansion (CTEs). As a result, additional stress derived from this difference is exhibited on the joint area, which also may cause cracks to form and/or delamination.